1. Field of the Invention
The present invention relates to liner materials and, more particularly the use of liner materials in integrated circuit fabrication.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e. g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e. g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. For example, low resistivity metal interconnects (e. g., aluminum and copper) provide conductive paths between the components on integrated circuits. Typically, the metal interconnects are electrically isolated from each other by an insulating material.
Additionally, a liner material often separates the metal interconnects from the insulating material. The liner material can be a barrier layer to inhibit the diffusion of the metal into the insulating material. Diffusion of the metal into the insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit, or render it inoperative. Alternatively, the liner material can be a nucleation layer (e. g., wetting layer) to which the interconnect metallization is adherent.
A combination of titanium (Ti) and/or titanium nitride (TiN), for example, is often used for the liner material. However, at high temperatures (e. g., temperatures greater than about 400xc2x0 C.) Ti and/or TiN may react with Al to form titanium tri-aluminide (TiAl3). The formation of the TiAl3 reduces the effective linewidth of the aluminum interconnects which undesirably increases the resistance of such interconnects and degrades the overall performance of the integrated circuit.
Therefore, a need exists in the art for integrated circuit metallization schemes including liner materials that are non-reactive with the metals used to form interconnects.
The present invention provides a method for metallizing integrated circuits. In one aspect, an integrated circuit is metallized by depositing liner material on a substrate followed by one or more metal layers. The liner material is selected from tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof. The liner material is preferably conformably deposited on the substrate using physical-vapor deposition (PVD). The one or more metal layers are conformably deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.
In another aspect, a damascene interconnect is fabricated. In one embodiment, a process sequence includes providing a substrate with one or more dielectric layers thereon. The one or more dielectric layers on the substrate, have apertures defined therein. Liner material selected from tantalum (Ta), tantalum nitride (TaN), niobium (Nb), niobium nitride (NbN), vanadium (V), vanadium nitride (VN), and combinations thereof is conformably deposited on the one or more dielectric layers. Thereafter, the damascene interconnect is formed when one or more metal layers are conformably deposited on the liner material. The liner material is preferably conformably deposited on the substrate using physical vapor deposition (PVD). The one or more metal layers are conformably deposited on the barrier layer using chemical vapor deposition (CVD), physical vapor deposition (PVD), or a combination of both CVD and PVD.